1. Field of the Invention
The present invention relates to a semiconductor chip having a field effect transistor unit and a semiconductor device in which such a semiconductor chip is mounted.
2. Description of the Related Art
FIGS. 1-3 show the construction of a semiconductor device of the prior art disclosed in Japanese Patent Laid-open No. 274116/96.
As shown in FIG. 1, this prior-art semiconductor device has semiconductor chips 105 joined to a chip mounting section formed in the center of package 101 that is provided with input-side lead wiring 102 and output-side lead wiring 103. Input matching circuit substrate 114, on which an input wiring pattern is formed, and output matching circuit substrate 115, on which an output wiring pattern is formed, are provided on insulating plate inside package 101.
Gate electrode 106, source electrode 107, and drain electrode 108 are formed on the surface of semiconductor chip 105 as shown in FIG. 2. Field effect transistor unit 112 is made up of three adjacent fingers of gate fingers, source fingers, and drain fingers. Gate fingers extend from gate bus bar 110, which is connected to gate electrode 106, source fingers extend from source electrode 107, and drain fingers extend from drain electrode 108. A reverse-side source electrode (not shown in the figure) that is connected to a power source is formed on the reverse surface of source electrode 107; and source electrode 107 and the reverse-side source electrode are connected by source via-holes 109. Interbonding electrodes 111, which are to be connected to the gates of other semiconductor chips, are connected to both ends of gate bus bar 110.
As shown in FIG. 3, gate electrode 106 of semiconductor chip 105 is connected to input matching circuit substrate 114 by means of metal wires 116, and drain electrode 108 is connected to output matching circuit substrate 115 by way of metal wires 117. In addition, interbonding electrodes 111 of adjacent semiconductor chips 105 are connected together by metal wiring 113, and the gate voltage between each of semiconductor chips 105 is thus maintained at a constant level.
Still higher output of field effect transistor units can be achieved in the above-described semiconductor device of the prior art by increasing the gate width of the field effect transistor units on the semiconductor chips. Methods of increasing the gate width, which is the total extension of the gate fingers, include methods in which the length of the gate fingers is increased and methods in which the gate fingers are increased in number. If gate fingers are made longer, however, the output efficiency (gain) of the field effect transistor unit drops. If, on the other hand, the gate fingers are increased in number, the increase in the number of gate fingers while keeping gate pitch uniform to prevent deterioration of thermal resistance not only mandates an increase in the area of the semiconductor chip, but also results in the occurrence of phase differences between the input signals due to increase in the width of the gate. Finally, increasing the gate width of a field effect transistor unit has the drawback that the areas of the gate electrode and drain electrode increase, and the area of the semiconductor chip therefore also increases considerably.
Reduction of source inductance, a type of parasitic component, was attempted in the prior art by supplying power to the source close to a field effect transistor unit by supplying power from the reverse side of the semiconductor chip by way of source via-holes formed in the source electrode. Unfortunately, the large area required for source electrodes in which source via-holes are formed has been an impediment to reducing the area of the overall semiconductor chip. In the previously described semiconductor device of the prior art, for example, a field effect transistor unit occupies 25% or less of the area of a semiconductor chip, and such a construction therefore impedes high integration of the semiconductor device and results in higher production costs.
Moreover, formation of source via-holes necessitates application of resist, light exposure, and development, followed by etching on the reverse side of the semiconductor chip. This processing gives rise to problems relating to the position for forming the source via-holes with respect to the source electrode, inadequate source power supply due to insufficient etching when forming via-holes, or conversely, via-holes that are larger than the source electrodes due to excessive etching when forming via-holes. Via-holes are filled by metal such as gold, but problems of inadequate source power supply have been encountered due to an insufficient amount of filler. A construction incorporating via-holes thus adversely affects reliability of the semiconductor device and complicates improvements in the productivity of semiconductor devices.